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MM74HC221A Dual Non-Retriggerable Monostable Multivibrator
September 1983 Revised September 2001
MM74HC221A Dual Non-Retriggerable Monostable Multivibrator
General Description
The MM74HC221A high speed monostable multivibrators (one shots) utilize advanced silicon-gate CMOS technology. They feature speeds comparable to low power Schottky TTL circuitry while retaining the low power and high noise immunity characteristic of CMOS circuits. Each multivibrator features both a negative, A, and a positive, B, transition triggered input, either of which can be used as an inhibit input. Also included is a clear input that when taken low resets the one shot. The MM74HC221A can be triggered on the positive transition of the clear while A is held LOW and B is held HIGH. The MM74HC221A is a non-retriggerable, and therefore cannot be retriggered until the output pulse times out. Pulse width stability over a wide range of temperature and supply is achieved using linear CMOS techniques. The output pulse equation is simply: PW = (REXT) (CEXT); where PW is in seconds, R is in ohms, and C is in farads. All inputs are protected from damage due to static discharge by diodes to VCC and ground.
Features
s Typical propagation delay: 40 ns s Wide power supply range: 2V-6V s Low quiescent current: 80 A maximum (74HC Series) s Low input current: 1 A maximum s Fanout of 10 LS-TTL loads s Simple pulse width formula T = RC s Wide pulse range: 400 ns to (typ) s Part to part variation: 5% (typ) s Schmitt Trigger A & B inputs enable infinite signal input rise or fall times
Ordering Code:
Order Number MM74HC221AM MM74HC221ASJ MM74HC221AN Package Number M16A M16D N16E Package Description 16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow 16-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide 16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide
Devices also available in Tape and Reel. Specify by appending the suffix letter "X" to the ordering code.
Connection Diagrams
Timing Component
Top View
Note: Pin 6 and Pin 14 must be hard-wired to GND.
(c) 2001 Fairchild Semiconductor Corporation
DS005325
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MM74HC221A
Truth Table
Inputs Clear L X X H H A X H X L B X X L Q L L Outputs Q H H
H H
L
H = HIGH Level L = LOW Level = Transition from LOW-to-HIGH = Transition from HIGH-to-LOW = One HIGH Level Pulse = One LOW Level Pulse X = Irrelevant

L

H

Logic Diagram
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MM74HC221A
Absolute Maximum Ratings(Note 1)
(Note 2) Supply Voltage (VCC) DC Input Voltage (VIN) DC Output Voltage (VOUT) Clamp Diode Current (IIK, IOK) DC Output Current, per pin (IOUT) DC VCC or GND Current, per pin (ICC) Storage Temperature Range (TSTG) Power Dissipation (PD) (Note 3) S.O. Package only Lead Temperature (TL) (Soldering 10 seconds) 260C 600 mW 500 mW
Recommended Operating Conditions
Min Supply Voltage (VCC) DC Input or Output Voltage (VIN, VOUT) Operating Temperature Range (TA) Maximum Input Rise and Fall Time (Clear Input) VCC = 2.0V VCC = 4.5V VCC = 6.0V 1000 500 400 ns ns ns 0 VCC V 2 Max 6 Units V
-0.5V to +7.0V -1.5V to VCC+1.5V -0.5V to VCC+0.5V 20 mA 25 mA 50 mA -65C to +150C
-40
+85
C
Note 1: Maximum Ratings are those values beyond which damage to the device may occur. Note 2: Unless otherwise specified all voltages are referenced to ground. Note 3: Power Dissipation temperature derating -- plastic "N" package: - 12 mW/C from 65C to 85C.
DC Electrical Characteristics
Symbol VIH Parameter Minimum HIGH Level Input Voltage VIL Maximum LOW Level Input Voltage VOH Minimum HIGH Level Output Voltage VIN = VIH or VIL |IOUT| 20 A Conditions
(Note 4)
VCC 2.0V 4.5V 6.0V 2.0V 4.5V 6.0V 2.0V 4.5V 6.0V 2.0 4.5 6.0 4.2 5.7 0 0 0 0.2 0.2 TA = 25C Typ 1.5 3.15 4.2 0.3 0.9 1.2 1.9 4.4 5.9 3.98 5.48 0.1 0.1 0.1 0.26 0.26 0.5 0.1 8.0 36 0.33 0.7 80 1.0 2.0 TA = -40 to 85C TA = -55 to 125C Guaranteed Limits 1.5 3.15 4.2 0.3 0.9 1.2 1.9 4.4 5.9 3.84 5.34 0.1 0.1 0.1 0.33 0.33 5.0 1.0 80 110 1.3 2.6 1.5 3.15 4.2 0.3 0.9 1.2 1.9 4.4 5.9 3.7 5.2 0.1 0.1 0.1 0.4 0.4 5.0 1.0 160 130 1.6 3.2 Units V V V V V V V V V V V V V V V V A A A A mA mA
VIN = VIH or VIL |IOUT| 4.0 mA |IOUT| 5.2 mA VOL Maximum LOW Level Output Voltage VIN = VIH or VIL |IOUT| 20 A 2.0V 4.5V 6.0V VIN = VIH or VIL |IOUT| 4.0 mA |IOUT| 5.2 mA IIN IIN ICC ICC Maximum Input Current (Pins 7, 15) Maximum Input Current (all other pins) Maximum Quiescent Supply VIN = VCC or GND Current (standby) Maximum Active Supply Current (per monostable) IOUT = 0 A VIN = VCC or GND R/CEXT = 0.5VCC 2.0V 4.5V 6.0V 6.0V VIN = VCC or GND 6.0V VIN = VCC or GND 4.5V 6.0V 6.0V 4.5V 6.0V
Note 4: For a power supply of 5V 10% the worst-case output voltages (VOH, and VOL) occur for HC at 4.5V. Thus the 4.5V values should be used when designing with this supply. Worst-case VIH and VIL occur at VCC = 5.5V and 4.5V respectively. (The VIH value at 5.5V is 3.85V.) The worst-case leakage current (IIN, ICC, and IOZ) occur for CMOS at the higher voltage and so the 6.0V values should be used.
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MM74HC221A
AC Electrical Characteristics
VCC = 5V, TA = 25C, CL = 15 pF, tr = tf = 6 ns Symbol tPLH tPHL tPHL tPLH tW tREM tWQ(MIN) tWQ Parameter Maximum Trigger Propagation Delay A, B or Clear to Q Maximum Trigger Propagation Delay A, B or Clear to Q Maximum Propagation Delay Clear to Q Maximum Propagation Delay Clear to Q Minimum Pulse Width A, B or Clear Minimum Clear Removal Time Minimum Output Pulse Width Output Pulse Width CEXT = 28 pF REXT = 2 k CEXT = 1000 pF REXT = 10 k 10 s 400 20 22 14 31 33 26 0 ns ns ns ns ns 25 42 ns Conditions Typ 22 Guaranteed Limit 36 Units ns
AC Electrical Characteristics
CL = 50 pF, tr = tf = 6 ns (unless otherwise specified) Symbol tPLH Parameter Maximum Trigger Propagation Delay A, B or Clear to Q tPHL Maximum Trigger Propagation Delay A, B or Clear to Q tPHL Maximum Propagation Delay Clear to Q tPLH Maximum Propagation Delay Clear to Q tW Minimum Pulse Width A, B, Clear tREM Minimum Clear Removal Time tTLH, tTHL Maximum Output Rise and Fall Time tWQ(MIN) Minimum Output Pulse Width tWQ Output Pulse Width CEXT = 28 pF REXT = 2 k REXT = 6 k (VCC = 2V) CEXT = 0.1 F REXT = 10 k Max CPD CIN CIN Power Dissipation Capacitance (Note 5) Maximum Input Capacitance (Pins 7 & 15) Maximum Input Capacitance (Other Inputs)
Note 5: CPD determines the no load dynamic power consumption, PD = CPD VCC2f + ICC VCC, and the no load dynamic current consumption, IS = CPD V CCf + ICC.
Conditions
VCC 2.0V 4.5V 6.0V 2.0V 4.5V 6.0V 2.0V 4.5V 6.0V 2.0V 4.5V 6.0V 2.0V 4.5V 6.0V 2.0V 4.5V 6.0V 2.0V 4.5V 6.0V 2.0V 4.5V 6.0V 5.0V 5.0V Min
TA = 25C Typ 77 26 21 88 29 24 54 23 19 56 25 20 57 17 12 169 42 32 197 48 38 114 34 28 116 36 29 123 30 21 0 0 0 30 8 7 1.5 450 380 1 1 87 12 6 20 10 0.9 1.1 75 15 13
TA = -40 to 85C TA = -55 to 125C Guaranteed Limits 194 51 39 229 60 46 132 41 33 135 42 34 144 37 27 0 0 0 95 19 16 210 57 44 250 67 51 143 45 36 147 46 37 157 42 30 0 0 0 110 22 19
Units ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns s ns ns
0.86 1.14
0.85 1.15
ms ms pF
20 10
20 10
pF pF
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MM74HC221A
Theory of Operation
FIGURE 1. TRIGGER OPERATION As shown in Figure 1 and the logic diagram before an input trigger occurs, the monostable is in the quiescent state with the Q output LOW, and the timing capacitor CEXT completely charged to VCC. When the trigger input A goes from VCC to GND (while inputs B and clear are held to VCC) a valid trigger is recognized, which turns on comparator C1 and N-channel transistor N11. At the same time the output latch is set. With transistor N1 on, the capacitor CEXT rapidly discharges toward GND until VREF1 is reached. At this point the output of comparator C1 changes state and transistor N1 turns off. Comparator C1 then turns off while at the same time comparator C2 turns on. With transistor N1 off, the capacitor CEXT begins to charge through the timing resistor, REXT, toward VCC. When the voltage across CEXT equals VREF2, comparator C2 changes state causing the output latch to reset (Q goes LOW) while at the same time disabling comparator C2. This ends the timing cycle with the monostable in the quiescent state, waiting for the next trigger. A valid trigger is also recognized when trigger input B goes from GND to VCC (while input A is at GND and input clear is at VCC2). The MM74HC221 can also be triggered when clear goes from GND to VCC (while A is at Gnd and B is at VCC6). It should be noted that in the quiescent state CEXTis fully charged to VCC causing the current through resistor REXT to be zero. Both comparators are "off" with the total device current due only to reverse junction leakages. An added feature of the MM74HC221 is that the output latch is set via the input trigger without regard to the capacitor voltage. Thus, propagation delay from trigger to Q is independent of the value of CEXT, REXT, or the duty cycle of the input waveform. The MM74HC221 is non-retriggerable and will ignore input transitions on A and B until it has timed out 3 and 4. RESET OPERATION These one shots may be reset during the generation of the output pulse. In the reset mode of operation, an input pulse on clear sets the reset latch and causes the capacitor to be fast charged to VCC by turning on transistor Q1 5. When the voltage on the capacitor reaches VREF2, the reset latch will clear and then be ready to accept another pulse. If the clear input is held LOW, any trigger inputs that occur will be inhibited and the Q and Q outputs of the output latch will not change. Since the Q output is reset when an input low level is detected on the Clear input, the output pulse T can be made significantly shorter than the minimum pulse width specification.
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MM74HC221A
Typical Output Pulse Width vs. Timing Components
Typical 1ms Pulse Width Variation vs. Supply
Typical Distribution of Output Pulse Width, Part to Part
Minimum REXT vs. Supply Voltage
Typical 1 ms Pulse Width Variation vs. Temperature
Note: R and C are not subjected to temperature. The C is polypropylene.
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MM74HC221A
Physical Dimensions inches (millimeters) unless otherwise noted
16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow Package Number M16A
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MM74HC221A
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
16-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide Package Number M16D
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MM74HC221A Dual Non-Retriggerable Monostable Multivibrator
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide Package Number N16E
Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications. LIFE SUPPORT POLICY FAIRCHILD'S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. 9 2. A critical component in any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. www.fairchildsemi.com
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